The present invention relates to a semiconductor memory and a process for fabricating the same, and more specifically, to a semiconductor memory in which a memory cell is formed on a semiconductor substrate to be constituted of a memory cell selecting transistor and a capacitor having a capacitor dielectric film formed of a ferroelectric material or a highly dielectric material in order to store information, and a process for fabricating the same.
Recently, a technology of a semiconductor memory having a capacitor dielectric film formed of a ferroelectric material or a highly dielectric material is actively developed. This semiconductor memory is so configured to store the information by utilizing polarization of the ferroelectric or highly dielectric material capacitor or whether or not an electric charge is stored in the highly dielectric material capacitor.
Referring to FIG. 7, there is shown a diagrammatic sectional view of a prior art memory cell. As shown in FIG. 7, source/drain diffused layers 102 are formed on a surface region of a semiconductor substrate (silicon substrate ) 101, and a gate electrode 103 is formed on a gate insulating film (not shown) formed on the semiconductor substrate 101. Thus, a field effect transistor constituting a memory cell selecting transistor is formed. A bit line is constituted of a first metal interconnection 105, which is electrically connected through a first plug (contact plug) 104 to one of the diffused layers 102 of the field effect transistor.
Above the field effect transistor, an interlayer insulator film, the first metal interconnection 105 and the first plug 104, are formed, and thereon, a capacitor is formed, which is constituted of a barrier layer 107, a lower electrode 111 and a ferroelectric material film (or highly dielectric material film) 112 and an upper electrode 113. The lower electrode 111 is electrically connected to the other of the diffused layers 102, through the barrier layer 107, the second plug (via plug) 106, the first metal interconnection 105 and the first plug 104. With this arrangement, a word line functions as the gate electrode 103 of the field electric transistor.
Incidentally, in FIG. 7, the interlayer insulator film 118 is formed of a first interlayer insulator film which is firmed on the semiconductor substrate and on which the first metal interconnection 105 is formed, and a second interlayer insulator film which is formed on the first interlayer insulator film and on which the barrier layer 107 is formed. However, the first and second interlayer insulator films are shown as a single interlayer insulator film 118.
The ferroelectric material film (high dielectric material film) 112 is formed of for example PZT (PbZrxTi1-xO3) or SBT (SrBi2Ta2O9), and formed by CVD (chemical vapor deposition) or another, as disclosed in for example JP-A-11-317500.
A capacitor cover insulating film 115 is formed on the capacitor, and a second metal interconnection 116 is formed as a plate line on the cover film 115.
In many cases, it is required to form the ferroelectric (high dielectric) material film in an oxidizing atmosphere or to anneal the ferroelectric (high dielectric) material film in an oxygen atmosphere after the ferroelectric (high dielectric) material film is formed, in order to stabilize the ferroelectric (high dielectric) material film. Because of this, the lower electrode 111 and the upper electrode 113 are formed of a platinum metal such as Pt, Ir and Ru, or alternatively a conductive oxide of platinum metal such as IrO2, RuO2, and SrRuO2. As shown in for example JP-A-08-236719, the barrier film 107 is provided to prevent the material of the plug from diffusing upward, and is formed of TiN in ordinary cases.
The first and second interconnections 105 and 116 are required to have an easy fine patterning, an excellent tight adhesion to SiO2 which forms the interlayer insulator film 118 and the capacitor cover film 115, and a low electric resistivity, and are formed of a multilayer film using WSi2, Ti, TiN or Al, for example.
On the second metal interconnection 116, a passivation film 117 is formed by forming a film of silicon nitride (SiNx) or silicon oxynitride film (SiOxNy) in a plasma CVD process. Incidentally, as described in JP-A-07-245237, it is known that a data rewriting anti-fatigue property in a semiconductor memory is greatly dependent upon the material which constitutes the lower electrode 111 in contact with the ferroelectric (or high dielectric) material film. If the lower electrode 111 is formed of Ir, Ru or a conductive oxide such as IrO2, RuO2, and SrRuO2, the data rewriting anti-fatigue property can be remarkably improved. Because of this, these materials are used to form the lower electrode 111.
In the case that the lower electrode 111 is formed of Ir, Ru or a conductive oxide such as IrO2, RuO2, and SrRuO2, it is known as shown in JP-A-06-326249 that in consideration of the tight adhesion with the lower electrode and the semiconductor substrate, the barrier layer is formed of TiN/Ti (lower layer of Ti and upper layer of TiN), and a ferroelectric (high dielectric) material film is deposited on a multilayer film which is formed by forming the barrier layer and the lower electrode in the named order.
However, the inventors have discovered a problem that when the multilayer film is formed by forming the barrier layer (formed of TiN/Ti) and the lower electrode in the named order on the semiconductor substrate having a plug formed therein (in which the plug is exposed at a surface of the interlayer insulator film), and then, the ferroelectric (high dielectric) material film is deposited on the multilayer film, the lower electrode is pealed off and is lifted up from the barrier layer (TiN/Ti), only in a region positioned above the plug.
Referring to FIG. 8A, there is shown a scanning electron microscope photograph of a section of one example, in which on a semiconductor substrate having a W plug formed therein, Ru/TiN/Ti is formed as a lower electrode/barrier layer structure, and then, PZT is deposited thereon in a CVD process at a temperature of 430 degrees Celsius. FIG. 8B is a diagrammatic view showing the feature of the photograph of FIG. 8A.
It would be seen from FIGS. 8A and 8B that PZT/Ru is pealed off and lifted up from TiN only in the region of the W plug. This lifting is considered as follows: Since PZT causes a large stress, a stress lifting up the PZT film is generated and concentrated in a region above the W plug, because of a thermodynamic relation among the semiconductor substrate, the W plug, the barrier layer, the lower electrode and the PZT film.
If the lower electrode above the W plug was pealed off and lifted up from the barrier layer, the capacitor of the memory cell above the W plug becomes defective, with the result that the yield of the semiconductor memory drops. In addition, reliability of the device characteristics drops dependently upon the degree of lifting-up from the barrier layer (the degree of connection insufficiency).